Call for papers

CASCADE is a new conference issued from the merge of COSADE and CARDIS that focuses on cryptographic implementations, physical attacks and embedded security. Its main goal is to encourage research and exchanges on cryptographic implementations and embedded security challenges. It welcomes contributions from the academia and industry and encourages in particular submissions by European PhD students willing to present their work while benefiting from:

• a constructive review process privileging technical and editorial feedback over taste,
• interactions with their research community without long-distance travels,
• exposition of industrial challenges that may generate new research discussions.

Papers can be submitted for review on two dates (one in the summer, one in the winter) for a single event in April.

Since 1994, CARDIS has been the venue for security experts from industry and academia to exchange on security of smart cards and related applications. Since 2010, COSADE has been an additional venue with dedicated focus on side-channel analysis, implementation attacks and secure designs. Starting in 2025, CARDIS and COSADE will merge into CASCADE, creating a unique annual international event to gather the community. For its first edition, CASCADE will take place in Saint-Étienne (France), from April 2 to 4, 2025.

Topics

The program committee is seeking original papers on all aspects of design, development, deployment, evaluation, and application of cryptographic implementations and secure embedded systems. You are invited to participate and submit your contributions to CASCADE'25. Submissions across a broad range of the development phase are encouraged, from exploratory research and proof-of-concept studies to practical applications and deployment. The program committee also invites survey and Systematization of Knowledge (SoK) papers that assess, systematize, and contextualize existing knowledge, as these papers offer significant value to our community. Topics of interest include, but are not limited to:

• Attacks and Countermeasures
• Physical and remote side-channel attacks & countermeasures
• Fault injection attacks and countermeasures
• Combined implementation attacks and countermeasures
• Micro-architectural attacks and countermeasures
• Hardware tampering and tamper-resistance
• Reverse engineering, (anti-)cloning, and (anti-)counterfeiting
• Hardware trojans and detection mechanisms
• Machine learning attacks and countermeasures
• Efficient and Secure Cryptographic Implementations
• Hardware & software cryptographic implementations
• Algorithmic aspects of cryptographic implementations
• Hardware security mechanisms, physically unclonable functions, true random number generator
• Cryptographic implementations for RISC-V architectures
• Post-quantum cryptographic implementations
• Lightweight cryptography
• White-box cryptography
• Tools and Methodologies
• Formal methods, techniques, and security models (for embedded security)
• Secure design and verification tools for hardware/software
• Security proofs in relevant models
• Computer-aided cryptographic engineering
• Domain-specific languages for cryptographic systems
• Automated and machine learning analysis frameworks
• Security evaluation platforms and tooling
• Open benchmarks for efficient and secure designs
• Applications
• Applications of secure embedded systems
• Trusted execution environments and trusted computing platforms
• Security of the internet of things
• Security of RISC-V architectures

Timeline

All deadlines are 23:59:59 Anywhere on Earth (AoE).

Summer Submission

• Paper submission : September 17, 2024October 1, 2024
• Result notification : December 1, 2024November 29, 2024

Winter Submission

• Paper submission : December 17, 2024
• Result notification : February 22, 2025

Instruction for authors

Submissions must be original, unpublished, anonymous and not submitted to journals or other conferences or workshops with proceedings. Submissions must be written in English and should be at most 20 pages in total (excluding references and appendices). There is no limit on the length of the bibliography and appendices when submitting. However, the reviewers are not required to read any appendices and the camera-ready version should be self-contained without appendices and strictly adhere to the page limit. Papers not meeting these guidelines risk rejection without consideration. All submissions will be blind-refereed. Submission implies the willingness of at least one of the authors to register and present the paper. The proceedings will be published in the Springer Lecture Notes in Computer Science (LNCS) series. Both submissions and accepted papers must follow the  LNCS default author instructions accessible on the Springer webpage: https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines .

Organization

General chairs

• Pierre-Louis Cayrel, UJM-Saint-Etienne, FR
• Brice Colombier, UJM-Saint-Etienne, FR
• Vincent Grosso, CNRS and UJM-Saint-Etienne, FR

Program chairs

• Matthieu Rivain, CryptoExperts, FR
• Pascal Sasdrich, Ruhr-Universität Bochum, DE
• e-mail contatct: cascade2025programchairs(at)gmail(dot)com